YQS40-8501M
YQS40-8501M
Supports 41.2Gbps aggregate bit rates
4x10.3Gbps 850nm VCSEL transmitter and PIN receiver
Maximum link length of 100m on OM3 MMF and 150m on OM4 MMF
Single MPO receptacle
Hot pluggable QSFP+ form factor
Power dissipation < 1.5W                     
All-metal housing for superior EMI performance
RoHS6 compliant (lead free)
Operating case temperature:
Commercial: 0ºC to +70°C
Quantity
Features
    • Supports 41.2Gbps aggregate bit rates
    • 4x10.3Gbps 850nm VCSEL transmitter and PIN receiver
    • Maximum link length of 100m on OM3 MMF and 150m on OM4 MMF
    • Single MPO receptacle
    • Hot pluggable QSFP+ form factor
    • Power dissipation < 1.5W                     
    • All-metal housing for superior EMI performance
    • RoHS6 compliant (lead free)
    • Operating case temperature:
Commercial: 0ºC to +70°C
                                                                     
 
Applications
    • 40GBASE-SR4
    • InfiniBand SDR/DDR/QDR


Standards
    • Compliant with QSFP+ MSA
    • Compliant with SFF-8636
    • Compatible with IEEE802.3ba


Description
The QSFP+ transceivers are designed for use in 40-Gigabit Ethernet links up to 100m over Multimode Mode Fiber.
The transceivers are compatible with QSFP+ MSA and SFF-8636. For further information, please refer to QSFP+ MSA and SFF-8636.

Module Block Diagram
   


Absolute Maximum Ratings
ParameterSymbolMin.TypicalMax.Unit
Power Supply VoltageVCC03.6V
Storage Temperature Ts-40+85°C
Relative HumidityRH085%
RX Input Average Power per LanePmax-3.5dBm

Recommended Operating Environment
ParameterSymbolMin.TypicalMax.Unit
Power Supply VoltageVCC3.133.33.46V
Power Supply CurrentICC750mA
Power DissipationPD2.5W
Operating Case TemperatureTC0+70°C
Aggregate Data Rate-41.25Gbps
Bit Rate per LaneBR10.3125Gbps

Electrical Characteristics
ParameterSymbolMin.TypicalMax.UnitNote
Transmitter Section
Input Differential ImpedanceRin90100110Ω
Differential Data Input SwingVin PP1801000mV1
Receiver Section
Differential Data Output SwingVoutPP300850mV







Notes:
  1. Connected directly to TX data input pins. AC coupling from pins into laser driver IC.


Optical Parameters
ParameterSymbolMin.TypicalMax.UnitNote
Transmitter Section
Lane Centre Wavelength (range)λC840860nm
Spectral Width (RMS) σ0.65nm
Average Optical Power per LanePout-7.6+2.4dBm1
OMA Power per LaneOMA-5.63dBm1
Laser Off Power per LanePoff---30dBm
Extinction RatioER3--dB2
Relative Intensity NoiseRIN---128dB/Hz
Optical Return Loss Tolerance--12dB
Transmitter eye mask definition
{X1, X2, X3, Y1, Y2, Y3}
Compliant with IEEE802.3ba
{0.23 0.34, 0.43, 0.27, 0.35, 0.4}
2
Receiver Section
Lane Center Wavelength (range)λC840860nm
Average Receiver Power per LaneRXPX-9.52.4dBm3
OMA Stressed Sensitivity per LaneRXsens-5.4dBm3
Los AssertLOSA-30--dBm
Los DessertLOSD---13dBm
Los HysteresisLOSH0.5-5dB
Overload per LanePin-max--2.4dBm3
Receiver Reflectance---12dB
Damage Threshold per Lane--3.5dBm

Notes:
1. The optical power is launched into 50/125µm MMF.
2. Measured with a PRBS 231-1 test pattern @10.3125Gbps.
3. Measured with a PRBS 231-1 test pattern @10.3125Gbps, ER=3dB, BER <10-12.


Pin Definitions





Pin Descriptions
PinSymbolDescriptionPlug Seq.Notes
1GroundGround11
2Tx2nTransmitter Inverted Data Input 3
3Tx2pTransmitter Non-Inverted Data Input 3
4GroundGround11
5Tx4nTransmitter Inverted Data Input 3
6Tx4pTransmitter Non-Inverted Data Input 3
7GroundGround11
8ModSelLModule Select 3
9ResetLModule Reset 3
10VccRx+3.3 V Power supply receiver 22
11SCL2-wire serial interface clock 3
12SDA2-wire serial interface data 3
13GroundGround11
14Rx3pTransmitter Non-Inverted Data Input3
15Rx3nTransmitter Inverted Data Input3
16GroundGround11
17Rx1pTransmitter Non-Inverted Data Input3
18Rx1nTransmitter Inverted Data Input3
19GroundGround11
20GroundGround11
21Rx2nTransmitter Inverted Data Input 3
22Rx2pTransmitter Non-Inverted Data Input 3
23GroundGround11
24Rx4nTransmitter Inverted Data Input 3
25Rx4pTransmitter Non-Inverted Data Input 3
26GroundGround11
27ModPrsLModule Present 3
28IntLInterrupt3
29VccTx+3.3 V Power supply transmitter 22
30Vcc1+3.3 V Power Supply 22
31LPModeLow Power Mode 3
32GroundGround11
33Tx3pTransmitter Non-Inverted Data Input3
34Tx3nTransmitter Inverted Data Input3
35GroundGround11
36Tx1pTransmitter Non-Inverted Data Input3
37Tx1nTransmitter Inverted Data Input3
38GroundGround11

Notes:
Plug Seq.: Pin engagement sequence during hot plugging.
1. Module ground pins GND are isolated from the module case.
2. VccRx, Vcc1 and VccTx are the receiver and transmitter power supplies and shall be applied concurrently.

Recommended Power Interface Circuit


Recommended Interface Circuit




Digital Diagnostic Functions 
The QSFP+ transceivers support the 2-wire serial communication protocol as defined in the QSFP+ MSA, which allows real-time access to the following operating parameters: 
    • Transceiver temperature 
    • Laser bias current 
    • Transmitted optical power
    • Received optical power
    • Transceiver supply voltage 
It also provides a sophisticated system of alarm and warning flags, which may be used to alert end-users when particular operating parameters are outside of a factory-set normal range. 
The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP+ transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP+ transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.
This clause defines the Memory Map for QSFP+ transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP+ devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in Figure 2 QSFP+ Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed.  For example, in Figure 2 upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0 and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.
For more detailed information including memory map definitions, please see the QSFP+ MSA Specification.

Mechanical Dimensions


Ordering information
Part NumberProduct Description
YQS40-8501M40Gbps QSFP+ SR4, 100m on MMF(OM3), MPO receptacle, 0ºC ~ +70ºC, With DDM.

References
1. SFF-8436 Specification for QSFP+ 10Gbs 4x Pluggable Transceiver.
2.SFF-8636 Specification for Management Interface for Cabled Environments.
3. IEE 802.3ba - PMD Type 40GBASE-SR4.

Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be specifically confirmed in writing by YOUTHTON before they become applicable to any particular order or contract. In accordance with the YOUTHTON policy of continuous improvement, specifications may change without notice. The publication of information in this data sheet does not imply freedom from patent or other protective rights of YOUTHTON or others. Further details are available from any YOUTHTON sales representative.

Contact Information
SHENZHEN YOUTHTON TECHNOLOGY CO., LTD.
ADD: F4, JINMA BUILDING, JINMA INDUSTRIAL PARK, SHIHUAN ROAD NO.4, SHIYAN STREET, BAOAN DISTRICT, SHENZHEN, CHINA
EMAIL: info@youthton.com