QSFP+ 40G 100m
YQS40-8501M
Supports 41.2Gbps aggregate bit rates
4x10.3Gbps 850nm VCSEL transmitter and PIN receiver
Maximum link length of 100m on OM3 MMF and 150m on OM4 MMF
Single MPO receptacle
Hot pluggable QSFP+ form factor
Power dissipation < 1.5W
All-metal housing for superior EMI performance
RoHS6 compliant (lead free)
Operating case temperature:
Commercial: 0ºC to +70°C
4x10.3Gbps 850nm VCSEL transmitter and PIN receiver
Maximum link length of 100m on OM3 MMF and 150m on OM4 MMF
Single MPO receptacle
Hot pluggable QSFP+ form factor
Power dissipation < 1.5W
All-metal housing for superior EMI performance
RoHS6 compliant (lead free)
Operating case temperature:
Commercial: 0ºC to +70°C
Quantity
Features
Applications
Standards
Description
The QSFP+ transceivers are designed for use in 40-Gigabit Ethernet links up to 100m over Multimode Mode Fiber.
The transceivers are compatible with QSFP+ MSA and SFF-8636. For further information, please refer to QSFP+ MSA and SFF-8636.
Module Block Diagram
Absolute Maximum Ratings
Recommended Operating Environment
Electrical Characteristics
Notes:
Optical Parameters
Notes:
1. The optical power is launched into 50/125µm MMF.
2. Measured with a PRBS 231-1 test pattern @10.3125Gbps.
3. Measured with a PRBS 231-1 test pattern @10.3125Gbps, ER=3dB, BER <10-12.
Pin Definitions
Pin Descriptions
Notes:
Plug Seq.: Pin engagement sequence during hot plugging.
1. Module ground pins GND are isolated from the module case.
2. VccRx, Vcc1 and VccTx are the receiver and transmitter power supplies and shall be applied concurrently.
Recommended Power Interface Circuit
Recommended Interface Circuit
Digital Diagnostic Functions
The QSFP+ transceivers support the 2-wire serial communication protocol as defined in the QSFP+ MSA, which allows real-time access to the following operating parameters:
The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP+ transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP+ transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.
This clause defines the Memory Map for QSFP+ transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP+ devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in Figure 2 QSFP+ Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed. For example, in Figure 2 upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0 and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.
For more detailed information including memory map definitions, please see the QSFP+ MSA Specification.
Mechanical Dimensions
Ordering information
References
1. SFF-8436 Specification for QSFP+ 10Gbs 4x Pluggable Transceiver.
2.SFF-8636 Specification for Management Interface for Cabled Environments.
3. IEE 802.3ba - PMD Type 40GBASE-SR4.
Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be specifically confirmed in writing by YOUTHTON before they become applicable to any particular order or contract. In accordance with the YOUTHTON policy of continuous improvement, specifications may change without notice. The publication of information in this data sheet does not imply freedom from patent or other protective rights of YOUTHTON or others. Further details are available from any YOUTHTON sales representative.
Contact Information
SHENZHEN YOUTHTON TECHNOLOGY CO., LTD.
ADD: F4, JINMA BUILDING, JINMA INDUSTRIAL PARK, SHIHUAN ROAD NO.4, SHIYAN STREET, BAOAN DISTRICT, SHENZHEN, CHINA
EMAIL: info@youthton.com
- Supports 41.2Gbps aggregate bit rates
- 4x10.3Gbps 850nm VCSEL transmitter and PIN receiver
- Maximum link length of 100m on OM3 MMF and 150m on OM4 MMF
- Single MPO receptacle
- Hot pluggable QSFP+ form factor
- Power dissipation < 1.5W
- All-metal housing for superior EMI performance
- RoHS6 compliant (lead free)
- Operating case temperature:
Applications
- 40GBASE-SR4
- InfiniBand SDR/DDR/QDR
Standards
- Compliant with QSFP+ MSA
- Compliant with SFF-8636
- Compatible with IEEE802.3ba
Description
The QSFP+ transceivers are designed for use in 40-Gigabit Ethernet links up to 100m over Multimode Mode Fiber.
The transceivers are compatible with QSFP+ MSA and SFF-8636. For further information, please refer to QSFP+ MSA and SFF-8636.
Module Block Diagram
Absolute Maximum Ratings
| Parameter | Symbol | Min. | Typical | Max. | Unit |
| Power Supply Voltage | VCC | 0 | 3.6 | V | |
| Storage Temperature | Ts | -40 | +85 | °C | |
| Relative Humidity | RH | 0 | 85 | % | |
| RX Input Average Power per Lane | Pmax | - | 3.5 | dBm |
Recommended Operating Environment
| Parameter | Symbol | Min. | Typical | Max. | Unit |
| Power Supply Voltage | VCC | 3.13 | 3.3 | 3.46 | V |
| Power Supply Current | ICC | 750 | mA | ||
| Power Dissipation | PD | 2.5 | W | ||
| Operating Case Temperature | TC | 0 | +70 | °C | |
| Aggregate Data Rate | - | 41.25 | Gbps | ||
| Bit Rate per Lane | BR | 10.3125 | Gbps |
Electrical Characteristics
| Parameter | Symbol | Min. | Typical | Max. | Unit | Note |
| Transmitter Section | ||||||
| Input Differential Impedance | Rin | 90 | 100 | 110 | Ω | |
| Differential Data Input Swing | Vin PP | 180 | 1000 | mV | 1 | |
| Receiver Section | ||||||
| Differential Data Output Swing | VoutPP | 300 | 850 | mV | ||
Notes:
- Connected directly to TX data input pins. AC coupling from pins into laser driver IC.
Optical Parameters
| Parameter | Symbol | Min. | Typical | Max. | Unit | Note |
| Transmitter Section | ||||||
| Lane Centre Wavelength (range) | λC | 840 | 860 | nm | ||
| Spectral Width (RMS) | σ | 0.65 | nm | |||
| Average Optical Power per Lane | Pout | -7.6 | +2.4 | dBm | 1 | |
| OMA Power per Lane | OMA | -5.6 | 3 | dBm | 1 | |
| Laser Off Power per Lane | Poff | - | - | -30 | dBm | |
| Extinction Ratio | ER | 3 | - | - | dB | 2 |
| Relative Intensity Noise | RIN | - | - | -128 | dB/Hz | |
| Optical Return Loss Tolerance | - | - | 12 | dB | ||
| Transmitter eye mask definition {X1, X2, X3, Y1, Y2, Y3} | Compliant with IEEE802.3ba {0.23 0.34, 0.43, 0.27, 0.35, 0.4} | 2 | ||||
| Receiver Section | ||||||
| Lane Center Wavelength (range) | λC | 840 | 860 | nm | ||
| Average Receiver Power per Lane | RXPX | -9.5 | 2.4 | dBm | 3 | |
| OMA Stressed Sensitivity per Lane | RXsens | -5.4 | dBm | 3 | ||
| Los Assert | LOSA | -30 | - | - | dBm | |
| Los Dessert | LOSD | - | - | -13 | dBm | |
| Los Hysteresis | LOSH | 0.5 | - | 5 | dB | |
| Overload per Lane | Pin-max | - | - | 2.4 | dBm | 3 |
| Receiver Reflectance | - | - | -12 | dB | ||
| Damage Threshold per Lane | - | - | 3.5 | dBm | ||
Notes:
1. The optical power is launched into 50/125µm MMF.
2. Measured with a PRBS 231-1 test pattern @10.3125Gbps.
3. Measured with a PRBS 231-1 test pattern @10.3125Gbps, ER=3dB, BER <10-12.
Pin Definitions
Pin Descriptions
| Pin | Symbol | Description | Plug Seq. | Notes |
| 1 | Ground | Ground | 1 | 1 |
| 2 | Tx2n | Transmitter Inverted Data Input | 3 | |
| 3 | Tx2p | Transmitter Non-Inverted Data Input | 3 | |
| 4 | Ground | Ground | 1 | 1 |
| 5 | Tx4n | Transmitter Inverted Data Input | 3 | |
| 6 | Tx4p | Transmitter Non-Inverted Data Input | 3 | |
| 7 | Ground | Ground | 1 | 1 |
| 8 | ModSelL | Module Select | 3 | |
| 9 | ResetL | Module Reset | 3 | |
| 10 | VccRx | +3.3 V Power supply receiver | 2 | 2 |
| 11 | SCL | 2-wire serial interface clock | 3 | |
| 12 | SDA | 2-wire serial interface data | 3 | |
| 13 | Ground | Ground | 1 | 1 |
| 14 | Rx3p | Transmitter Non-Inverted Data Input | 3 | |
| 15 | Rx3n | Transmitter Inverted Data Input | 3 | |
| 16 | Ground | Ground | 1 | 1 |
| 17 | Rx1p | Transmitter Non-Inverted Data Input | 3 | |
| 18 | Rx1n | Transmitter Inverted Data Input | 3 | |
| 19 | Ground | Ground | 1 | 1 |
| 20 | Ground | Ground | 1 | 1 |
| 21 | Rx2n | Transmitter Inverted Data Input | 3 | |
| 22 | Rx2p | Transmitter Non-Inverted Data Input | 3 | |
| 23 | Ground | Ground | 1 | 1 |
| 24 | Rx4n | Transmitter Inverted Data Input | 3 | |
| 25 | Rx4p | Transmitter Non-Inverted Data Input | 3 | |
| 26 | Ground | Ground | 1 | 1 |
| 27 | ModPrsL | Module Present | 3 | |
| 28 | IntL | Interrupt | 3 | |
| 29 | VccTx | +3.3 V Power supply transmitter | 2 | 2 |
| 30 | Vcc1 | +3.3 V Power Supply | 2 | 2 |
| 31 | LPMode | Low Power Mode | 3 | |
| 32 | Ground | Ground | 1 | 1 |
| 33 | Tx3p | Transmitter Non-Inverted Data Input | 3 | |
| 34 | Tx3n | Transmitter Inverted Data Input | 3 | |
| 35 | Ground | Ground | 1 | 1 |
| 36 | Tx1p | Transmitter Non-Inverted Data Input | 3 | |
| 37 | Tx1n | Transmitter Inverted Data Input | 3 | |
| 38 | Ground | Ground | 1 | 1 |
Notes:
Plug Seq.: Pin engagement sequence during hot plugging.
1. Module ground pins GND are isolated from the module case.
2. VccRx, Vcc1 and VccTx are the receiver and transmitter power supplies and shall be applied concurrently.
Recommended Power Interface Circuit
Recommended Interface Circuit
Digital Diagnostic Functions
The QSFP+ transceivers support the 2-wire serial communication protocol as defined in the QSFP+ MSA, which allows real-time access to the following operating parameters:
- Transceiver temperature
- Laser bias current
- Transmitted optical power
- Received optical power
- Transceiver supply voltage
The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP+ transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP+ transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.
This clause defines the Memory Map for QSFP+ transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP+ devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in Figure 2 QSFP+ Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed. For example, in Figure 2 upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0 and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.
For more detailed information including memory map definitions, please see the QSFP+ MSA Specification.
Mechanical Dimensions
Ordering information
| Part Number | Product Description |
| YQS40-8501M | 40Gbps QSFP+ SR4, 100m on MMF(OM3), MPO receptacle, 0ºC ~ +70ºC, With DDM. |
References
1. SFF-8436 Specification for QSFP+ 10Gbs 4x Pluggable Transceiver.
2.SFF-8636 Specification for Management Interface for Cabled Environments.
3. IEE 802.3ba - PMD Type 40GBASE-SR4.
Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be specifically confirmed in writing by YOUTHTON before they become applicable to any particular order or contract. In accordance with the YOUTHTON policy of continuous improvement, specifications may change without notice. The publication of information in this data sheet does not imply freedom from patent or other protective rights of YOUTHTON or others. Further details are available from any YOUTHTON sales representative.
Contact Information
SHENZHEN YOUTHTON TECHNOLOGY CO., LTD.
ADD: F4, JINMA BUILDING, JINMA INDUSTRIAL PARK, SHIHUAN ROAD NO.4, SHIYAN STREET, BAOAN DISTRICT, SHENZHEN, CHINA
EMAIL: info@youthton.com